The present invention pertains in general to a multiple processor system and, more particularly, to the distributed memory structure associated therewith.
In order to increase the processing capability of any system, multiple processor arrays have been utilized. Typically, these multiple processor arrays are comprised of independent central processing units (CPUs) which are disposed in an array with each having a local bus with local peripheral units disposed thereabout. The local buses of each of the CPUs is then interfaced with a global bus. In turn, the global bus is interfaced with a system bus. One type of system bus is a VME bus.
When handling data flow between the system bus and each of the CPUs in the array of processors, traffic must be routed over the global bus. In order for information to be transmitted either from the processors to the system bus or from the system bus to the processors, there must be some type of arbitration. Typically, a bus request is sent out to the global bus control system and then the bus request granted to that requesting device. Data can then be transmitted over the bus in the appropriate manner. This is a conventional operation. However, the global bus becomes the limiting factor in transfer of data between processors and the system bus, and even between adjacent processors on the global bus. This is due to the fact that only one device can occupy the global bus at a given time.
One type of CPU that has been used widely is a Digital Signal Processor (DSP). These processors execute instructions at a very high rate but, unfortunately, like most processors, the architecture of the processor will determine the limitations of that processor with respect to communicating with the global bus, communicating with other processors and handling interrupts. Typically, most DSPs are designed for single chip use and must be provided with another layer of infrastructure in order to be incorporated into an array of microprocessors.
In a multi-processor system, multiple processors must access and share common memory within the xe2x80x9cglobalxe2x80x9d address space. This is typically facilitated by providing a common global memory, with each storage location in the global memory occupying a defined portion of the global address space. In order to transfer information to a processor across a global bus, the resource having control of the bus, the bus master, will transfer data into the global memory and then transmit a command to the local processor to retrieve that information, which is facilitated by the processor accessing data from the global memory. However, in addition to there being a global address space, each processor has associated therewith its own local address space which is reserved for local resources associated with that processor. These local resources and this local address space are not accessible by the other processors or the other resources on the global bus. These local resources within that local address space are only accessible by the associated processor itself. Of course, a portion of the local address space, the local address space being defined as an address within an addressing capability of the processor, is associated with the global address space such that the processor need only generate an address within that portion to directly access the global resources such as the global memory.
The present invention disclosed and claimed herein comprises a method and apparatus for transferring data between a global resource on a global bus in a multi-processor system and the local bus of a plurality of processor nodes, each having a processor associated therewith. A plurality of memory devices are provided, each disposed between the global bus and the local bus of an associated one of the processor nodes. A portion of the global address space of the global address bus is designated to each of the memory devices. A portion of the local address space of the local bus of each of the processor nodes is designated as belonging to the associated memory device for that processor node. Data is transferred between the global resource and a select one of the memory devices within a portion of the global address space associated therewith with data also being transferred between the memory device and the associated processor within the portion of the local address space associated therewith.
In another aspect of the present invention, the transfer of data between the processor and the global resource via the memory device is performed in response to the operation of transferring data to the memory device from one of the processors or the global resource.
In a further aspect of the present invention, each of the memory devices is comprised of a dual-ported memory, having a first memory port associated with the global bus and a second memory port associated with the local bus for the associated processor node. The first port is addressable from the global bus within the global address space of the global bus and the second port is addressable from the associated local bus within the local address space of the local bus. Each processor has associated therewith an interrupt input with the associated dual-ported memory, including a portion thereof for generating an interrupt in response to data being transferred thereto on the global bus side of the memory device from the global resource.